The PX1011B is a high-performance, low-power, single-lane PCI Express electrical PHYsical layer (PHY) that handles the low level PCI Express protocol and signaling. The PX1011B PCI Express PHY is ...
Silicon-proven PCIe Subsystem Offers High Performance, Low Risk Alternative to Traditional ASIC, FPGA Options Santa Clara, Calif.—ChipX, the Structured ASIC leader, today announced the CX6100 family ...
The IntelliProp IPC-GZ197A-ZM Gen-Z Physical Layer for PCIe is an IP Core that allows companies to attach a Gen-Z core to a PCIe Phy. The IPC-GZ197A-ZM is compliant with the Gen-Z 1.1 Physical ...
As data rates continue to increase, maintaining reliable links requires careful coordination between the PHY and controller ...
CHESTNUT RIDGE, N.Y., Feb. 23, 2021 /PRNewswire/ -- Teledyne LeCroy introduced the CrossSync™ PHY interposers and software options, enabling the first-ever link between an oscilloscope and a protocol ...
PCI Express (PCIe) is a typical protocol that consists of several distinct layers: physical with logical sub-block, data link, and transaction. Each of the layers actually is a separate protocol ...
Connectivity is becoming a bottleneck in the age of AI. To unclog the interconnects between processors, accelerators, and memory, high-speed serial interfaces based on the PCIe Gen 6 bus are in the ...
San Jose, California -- January 23, 2006-- HiTech Global, the global distributor of HiTech products, has signed an agreement to distribute and market Genesys Logic’s PCI Express products in North ...
SAN JOSE, Calif.--(BUSINESS WIRE)--PLDA, the industry leader in PCI Express® and interface IP solutions and M31, a global silicon intellectual property (IP) boutique, today announced that their ...
The new PHY VIP enables comprehensive and fast verification of the physical layer for complex protocols such as PCIe 5.0, USB3/4, DDR5, LPDDR5, HBM and MIPI CSI-2 and DSI 2.0 SAN JOSE, ...
PCI-SIG has announced the next generation of its interconnect standard, PCIe 8.0, aimed at supporting growing demands from ...
As a result of the innovations taking place in CPUs, GPUs, accelerators, and switches, the interface in hyperscale datacenters now requires faster data transfers both between compute and memory and ...
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